---------------------------------------------------------------------------
-- Company     : Vim Inc
-- Author(s)   : Fabien Marteau
-- 
-- Creation Date : 24/04/2008
-- File          : intercon.vhd
--
-- Abstract : Intercon is the component where we do
--            the address decoding
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

---------------------------------------------------------------------------
Entity intercon is 
---------------------------------------------------------------------------
port 
(
		-- general clock and reset
		gls_reset_n   : in std_logic ;
		gls_clock     : in std_logic ;

		-- Master wrapper port
		wbm_reset_n   : out std_logic ;
		wbm_clk       : out std_logic ;

		wbm_address   : in std_logic_vector( 15 downto 0);
		wbm_readdata  : out std_logic_vector( 7 downto 0);
		wbm_writedata : in std_logic_vector( 7 downto 0);
		wbm_strobe    : in std_logic ;
		wbm_write     : in std_logic ;
		wbm_ack       : out std_logic ;
		wbm_cycle     : in std_logic ;

		-- Slave LED port
		wbs_reset_n   : out std_logic ;
		wbs_clk       : out std_logic ;

		wbs_writedata : out std_logic_vector(7  downto 0);
		wbs_readdata  : in std_logic_vector( 7 downto 0);
		wbs_strobe    : out std_logic ;
		wbs_write	    : out std_logic ;
		wbs_ack	      : in std_logic;

		-- Slave pwm port
		wbs_reset_n_pwm : out std_logic ;
		wbs_clk_pwm     : out std_logic ;

		wbs_address_pwm   : out std_logic;
		wbs_writedata_pwm : out std_logic_vector( 7 downto 0);
		wbs_readdata_pwm  : in  std_logic_vector( 7 downto 0);
		wbs_strobe_pwm    : out std_logic ;
		wbs_write_pwm     : out  std_logic ;
		wbs_ack_pwm       : in  std_logic 

);
end entity;


---------------------------------------------------------------------------
Architecture intercon_1 of intercon is
---------------------------------------------------------------------------
	signal led_cs : std_logic ;
	signal pwm_cs : std_logic ;
	signal cs : std_logic_vector( 1 downto 0);
begin

	-- clock and reset connection
	wbm_clk     <= gls_clock;
	wbm_reset_n <= gls_reset_n;

	wbs_clk     <= gls_clock;
	wbs_reset_n <= gls_reset_n;

	wbs_clk_pwm     <= gls_clock;
	wbs_reset_n_pwm <= gls_reset_n;
	
	-- address decoding (asynchrone but ...)
	led_cs <= '1' when wbm_address = x"1300" and wbm_strobe = '1' else '0';
	pwm_cs <= '1' when (wbm_address = x"1302" or wbm_address = x"1303")
											and wbm_strobe = '1' else '0';
	wbs_address_pwm <= wbm_address(0) when pwm_cs = '1' else '0';
	
	-- slave LED connection
	wbs_writedata <= wbm_writedata when led_cs = '1' else (others => '0');
	wbs_strobe    <= wbm_strobe and led_cs;
	wbs_write     <= wbm_write  and led_cs;

	-- Slave pwm connection
	wbs_writedata_pwm <= wbm_writedata when pwm_cs = '1' else (others => '0');
	wbs_strobe_pwm    <= wbm_strobe and pwm_cs;
	wbs_write_pwm     <= wbm_write  and pwm_cs;

	cs(0) <= led_cs;
	cs(1) <= pwm_cs;


	-- master wrapper connection
	with cs select
	wbm_readdata  <= wbs_readdata     when "01",
									 wbs_readdata_pwm when "10",
									 (others => '0')  when others;
	with cs select
	wbm_ack <= wbs_ack     when "01",
						 wbs_ack_pwm when "10",
						 '0'         when others;
	
end architecture intercon_1;

